The present invention relates to a metal wiring of a semiconductor device, and more particularly, to a metal wiring in a semiconductor device by forming an Al layer without creating voids therein by controlling the Al-growth characteristics, and a method for forming the same.
For highly integrated semiconductor devices, high-speed is an increasingly important requirement, and therefore memory cells are formed in a stacked structure. Moreover, the metal wiring used for carrying electric signals to the cells is also formed in a multi-layer structure. The metal wiring having the multi-layer structure provides advantageous design flexibility and allows more leeway in setting the margins for the wiring resistance, the current capacitance, etc.
Aluminum (Al) is widely used as a material for the metal wiring in a highly integrated semiconductor device, for its superior electrical conductivity and forming efficiency when applied in a fabrication process. The Al is used as a diffusion barrier layer, since it can ensure electric characteristics of the semiconductor device.
Hereinafter, a method is described for forming the metal wiring in a semiconductor device according to prior art, which uses Al as the material of a metal wiring referring to FIG. 1.
A first oxide layer 140 and a second oxide layer 160 are sequentially formed over the semiconductor substrate 100 on which a conductive patterns 110 and a interlayer insulating layer 120 are formed. Until the conductive patterns 110 is exposed, the first oxide layer 140 and the second oxide layer 160 are etched so as to form via-holes 171 defining via contact regions and trenches 172 defining metal wiring regions, thereby forming dual-type damascene pattern 170 including the via-holes 171 and the trenches 172.
A diffusion barrier layer 180 is formed on the second oxide layer 160 including the damascene pattern 170. Herein, the diffusion barrier layer 180 is formed as a stacked layer composed of a Ti layer 181 and a TiN layer 182. Al is filled in the damascene pattern 170 on which the diffusion barrier layer 180 is formed, thereby forming via contacts 193 within the via-holes 171 and the metal wirings 194 composed of Al layer within the trenches 172.
As described above according to prior art, upon forming the metal wiring using Al, the diffusion barrier layer 180 is used for preventing the electric characteristics from being degraded due to high bonding force with the oxide layer and movement and diffusion of electrons from the metal wiring. The diffusion barrier layer 180 is formed by using the Ti layer 181 and the TiN layer 182 or a stacked layer of both.
Meanwhile, as the design rule of the semiconductor device decrease, the line width of the via-hole 193 and the trench 194 would also decrease. However, if the stacked layer of the Ti layer 181 and the TiN 182 layer is formed as the diffusion barrier layer 180 on the surface of the via-hole 193 and the trench 194 at the time that the line width of the via-hole 193 and the trench 194 decreases, the margin of the line width of the via-hole 193 and the trench 194 also decreases.
This type of margin reduction of the line-width of the via-hole 193 and the trench 194 caused by the diffusion barrier layer 180 formed as the stacked layer of the Ti layer 181 and the TiN layer 182 causes overhang when depositing Al in the via-hole 193 and the trench 194 to form metal wiring. As a result, Al is not entirely filled in the via-hole 193 and the trench 194, and therefore voids are often generated within the via-hole 193 and the trench 194.
If the voids are generated on lower portion of the via-hole 193 and the trench 194 due to reduction in the line-width of the via-hole 193 and the trench 194, it causes errors in operational characteristics of the semiconductor device or decrease the total yield of the semiconductor device.